Field of the Invention
The present invention relates to a dynamic semiconductor memory circuit, and more particularly to a dynamic memory circuit having a number of memory cells each with predetermined data hold characteristics.
Description of the Prior Art
Due to the capacitive nature of the memory cells in a dynamic memory circuit, the circuit must be periodically refreshed in order to maintain a predetermined charge level in the cells. The refresh operation is usually performed by reading and amplifying data corresponding to the electric charge stored in the capacitive element, and rewriting the information into the memory cell by supplying another electric charge, representative of the same data, to the same capacitive element. The time interval between refreshes without data loss is referred to as "data hold time". For example, a dynamic random access memory circuit (DRAM) of 16 Mbit with a required 2K refreshes per refresh cycle at an upper operational temperature limit of 70.degree. C. has a standard data hold time of 32 ms. The number of required refreshes per refresh cycle is dependent upon the number of memory cells in the circuit. As the number of cells increases, the number of refreshes increases and consequently, the required data hold time increases. If the number of refreshes is increased to 4K refreshes per cycle, the data hold time is 64 ms. Since data hold characteristics depend on leak current in a junction portion of the memory cell, temperature is an important factor and, in general, data hold time doubles when temperature decreases by 10.degree. C. Therefore, when a data hold test is performed at normal temperature (20.degree. C.), the required time greatly increases.
Generally, there are two types of data hold tests, a static test and a disturb test. In the static test, data is merely written into all memory cells, held therein while all circuit operations are stopped, and then read back for comparison to the original data. In the disturb test, a certain cell is tested by writing data into that cell, and "disturbing" nearby memory cells by driving their word and bit lines to select and non-select levels while the tested memory cell is holding the data. The held data is then read back to determine the influence of the level switching of other memory cells, on the memory content of the tested memory cell.
The static test determines whether data is correctly written, by writing data into all memory cells, holding the data and reading it, as mentioned above. Since the required test time is the sum of the data hold time and the data write and read times, it is proportional to the data hold time. In the case of the above mentioned 16 Mbit DRAM, the standard data hold time of the memory with 4K refreshes is 64 ms at 70.degree. C. Considering the fact that the data hold time doubles with a temperature reduction of 10.degree. C., data hold times of about 2 seconds at normal temperature (20.degree. C.) are not uncommon. It is therefore necessary to verify by testing, that data can be held for 3.0 seconds, considering a safety margin of 1.5 times. When the time necessary to write or read data to or from a memory cell is 200 ns, the write and read times for a memory of 16 Mbit are each 200 (ns).times.16 (Mbits)= 3.2 (s). In order to write and read both true and false (0,1) signals, each write and read operation must be performed twice. Therefore, the total write and read time becomes 4.times.3.2(s)=12.8 seconds. The total test time for a 3.0 second data hold time becomes 18.8 seconds, where two 3-second hold times are included. As memory sizes increase, this total test time also increases and test times of several tens of seconds are not uncommon.
In the disturb test the required test time is proportional to memory capacity. That is, since the test in the disturb test is performed for all word lines, test time becomes (data hold time).times.(number of word lines).
For example, a disturb test for a 16 Mbit DRAM with 4K refreshes at normal temperature (20.degree. C.) with a data hold time of 3.0 seconds and a cycle time of 200 ns, will be now examined. In the disturb test, all memory cells must be refreshed for every data hold (i.e., each word line). Thus, one word line test time is 200 (ns).times.4 (K cycles)+3.0(second) which is about 3.0 seconds. Therefore, a total test time becomes [200 (ns).times.4 (K cycles)+3.0 (s)].times.4 (K cycles)+3.2.times.2=12009.4 seconds (about 3 hours 20 minutes), where write time and read time are each 3.2 seconds. This total test time is doubled when both 1's and 0's are tested, and therefore becomes 24018.18 seconds (about 6 hours 40 minutes). This test time is very long compared with that of the static test.